Asynchronous transfer mode (ATM) configured networks allow high-speed data, voice and video communications to be conducted between endpoint computer systems. ATM networks, which are based on the transmission of fixed-length data packets, have proven to be extremely useful because they combine the benefits of both a switched network (i.e., constant transmission delay, guaranteed capacity) and a packet switched network (i.e., flexibility and efficiency for intermittent traffic).
Current ATM standards are defined by the International Telecommunication Union and (ITU) ATM Forum specifications, which are herein incorporated by reference. As is common in contemporary communications protocols, several protocol layers are used to functionally divide the communications task within an ATM network. The ATM protocol layers are similar in scope to the Open System Interconnection (OSI) reference model that is defined by the International Standardization Organization (ISO).
In ATM networks, a variable length protocol data unit (PDU) defines the data to be shared between higher protocol layers, such as the application layer software programs operating at the endpoint computer systems. A typical PDU includes the data to be shared along with additional header and trailer information. To transmit the PDU over an ATM configured network, each PDU is further divided into fixed-length transmission units, known as cells. A typical cell is 53 bytes long and includes a 5-byte header containing its' connection identifier and a 48-byte payload. Thus, a 480-byte PDU would be divided into ten cells, each cell having a 48 byte payload, or one tenth of the total PDU.
During transmission, a cell is sent from one endpoint computer system to another through a virtual circuit within the interconnecting ATM network. A virtual circuit acts as a logically independent connection with another network node. A virtual circuit typically is a concatenation of communication links established between the two endpoints where higher layer protocols are accessed. By definition, ATM cells are transmitted in a sequence over an established virtual circuit. As such, the virtual circuit exists throughout the transmission of a PDU. One of the advantages of an ATM configured network is that a number of virtual circuits can be established over a single wire or fiber connecting the sending computer system to the network by time-division multiplexing the cells from different PDUs.
Typically, an ATM Network Interface Card (NIC) and accompanying software are provided within the sending (or receiving) endpoint computer systems to transmit (or receive) the cells of a PDU over a virtual circuit. In terms of the OSI reference protocol model, a typical NIC provides link layer functionality by supplying cells in a specific sequence to the physical layer of the ATM network. In contrast, the virtual circuits within the ATM network are typically established at a higher level layer, as are the PDUs and information therein.
FIG. 1A is a block diagram illustrating a typical ATM network 10 having a first endpoint computer labeled host 12, a network 14, and one or more additional endpoint computers labeled end stations 16. Within network 14 there are illustrated, by way of dashed connecting lines, a plurality of virtual circuits 18 that represent the communication channels established between host 12 and end stations 16 during an ATM communication. By way of example, network 14 may include one or more telecommunications and/or data networks, having switching devices, routing devices, and dedicated communication lines and/or fibers that are capable of providing a communication link between host 12 and end stations 16. Host 12 and end stations 16 may, for example, be personal computer systems, workstations, mainframes, or other like processing devices that are capable of sending and receiving ATM PDUs.
FIG. 1B is a block diagram that illustrates one possible configuration of an endpoint computer system (such as host 12 in FIG. 1A) having a processor 20, a host bus 22, a system memory 24, a PCI controller 26, a PCI bus 28, a NIC 30, and an optional SCSI interface 32 and SCSI device 34. Processor 20 may be a microprocessor or central processing unit (CPU) configured to access system memory 24. System memory 24 may be a dynamic random access memory (DRAM) that is accessed via host bus 22 or by way of another interconnecting circuit. SCSI device 34 may be a secondary data storage device, such as a disk drive unit, that can be accessed by processor 20 by way of host bus 22, PCI controller 26, PCI bus 28, and SCSI interface 32. As shown, processor 20 can also access network 14 by way of PCI bus 28 and NIC 30. It is recognized that additional processors, other devices, additional buses, etc., can be connected to either the host bus or to the PCI bus as is common in modern computing configurations.
In a typical endpoint computer system, when the higher level protocol and/or application layers require a PDU to b e transmitted over network 14 to another endpoint computer system several process steps occur. First, a virtual circuit is established by processor 20 via NIC 30. Next, the PDU is stored in system memory 24 by processor 20. Following that, NIC 30 is directed by processor 20 to complete the desired PDU transmission. To complete the transmission of the PDU, NIC 30 fetches the cells within the PDU and transmit these cells one-by-one over a virtual circuit in network 14.
On the receiving end of th e ATM network is another endpoint computer. This endpoint computer also includes a NIC 30 that receives the incoming cells in the same order as they were transmitted. As the cells are received, it is the task of NIC 30 and/or processor 20 to reassemble the cells into th e original PDU. The reassembled PDU can then be provided to the higher layer applications. As such, one important consideration in the design and operation of a NIC and its associated software is the reassembly of the PDU and the transferring of either the received cells and/or a reassembled PDU from the NIC to the system memory in the computer. A NIC that is able to effect the transfer of a PDU to system memory efficiently is valuable.
Conventional NICs can b e divided into one of two groups based upon their reassembly methods. In the first reassembly method, the NIC provides each cell as it arrives to the system memory. The NIC manages reassembly buffers in system memory, sending a received cell to the appropriate buffer based on its virtual circuit identifier and thereby reassembling the PDU. This type of reassembly is used, for example, in the IDT77201 product available from Integrated Device Technology Inc. of Santa Clara, Calif. While this type of operation tends to reduce the amount of memory required on the NIC, it also tends to place an unacceptable load or "transfer burden" on the interconnecting devices and buses which are required during the sequential transferring of each of the received cells from the NIC to the system memory. That is, the overhead with transferring a cell at a time from the NIC to system memory may be high.
The second reassembly method attempts to r educe the burden on the interconnecting devices and buses by providing enough memory on-board the NIC to store a complete PDU before transfer. Thus, with this type of NIC the entire PDU is reassembled in the NIC's local memory and then is transferred at one time from the NIC to the host memory. This type of reassembly is used, for example, in the 5930 product available from Adaptec Inc. of Milpitas, Calif. While this type of NIC tends to reduce the "transfer burden" by minimizing the amount of time required to transfer the reassembled PDU from the NIC to the host memory, the amount of on-board local memory required to support a number of virtual circuits (i.e., memory for simultaneously storing and reassembling a number of PDUs) can reduce the overall effectiveness of the NIC, and/or greatly increase the NIC's cost, power consumption and size.
Thus, what is desired are improved methods and apparatus for PDU reassembly that effectively reduce the "transfer burden" on the interconnecting devices, buses, and/or the host processor, while also minimizing the amount of on-board memory required for the NIC.